# Besiege – Guide to Logic Gates, Boolean

A very basic guide in digital electronics, here I will cover the basics about Boolean algebra and circuits with logic gates for Besiege

## Guide to Logic Gates, Boolean

### Introduction

V1.0 brought a gift from the heavens, four blocks that will allow us to sequence and automate various aspects from our machines. but not everyone has knowledge about the different logic gates or the Boolean algebra under which they work.

This guide will cover the basics of Boolean algebra, the different kinds of logic gates and a few extra things that will make your life easier.

### The Logic Gates

#### Or

The OR logic gate will have a high (1) output when at least one of its inputs also has a high value. Its formula is A+B=Q.

#### And

The AND logic gate will have a high output when both its inputs have a high value. Its formula is A×B=Q.

#### Not

The NOT gate, also known as the inverter will give the opposite value of its input as his output. The formula is A´=Q (the actual symbol would be an A with a line over it, but I didn´t found how to do it).

#### Nor

The NOR logic gate will have a high (1) output when both its inputs have a low value. Its formula is (A+B)´=Q.

#### Nand

The NAND logic gate will have a high output when at least one of its inputs has a low value. Its formula is (A×B)´=Q.

#### XOR

The XOR logic gate will have a high output when both inputs have different values. Its formula is A⊕B=Q.

#### XNOR

The XOR logic gate will have a high output when both inputs have the same value. Its formula is (A⊕B)´=Q.

### Boolean Algebra and Karnaugh Maps

Now that you know your Boolean operations, this will be your design phase. Now its time for you to make the truth table for your circuit, a truth table includes all possible combinations of the circuit input variables and the output value (only one output per table, more output variables mean one formula for each one, and thus a different circuit).

Now comes one of the tricky parts, as there are two complementary ways of deducting the formula from the truth table, those are Minterms (logical AND) and Maxterms (logical OR), as expressed in De Morgan´s Laws.

(A+B)´=A´×B´ and (A×B)´=A´+B´

The objective is to get the formula to its minimal expression to simplify the design.

### The Importance of Using a Clock

While the title seems a joke, believe me, it won’t be when you are trying large scale sequenced actions. A clock is an oscillator which goes from low to high outputs at a predefined frequency, the amount of full cycles per second is measured in Hertz (Hz=1/Time).

It is advisable for both high and low states to have the same duration.

So why is this mandatory for large computing and sequences?? because it will synchronize your whole machine when the clock is in its low state no computing will be done.

### Latches and Flip Flops

Maybe one of the most useful things you can build, these are memory circuits that store a bit of data. I won’t describe the whole theory behind this electronic devices, for that, I will leave a link at the end of this section, now I will cover just some basics, for now, you just need to know than latches (unlike Flip Flops) dont need a clock to work, they are asynchronous components. Depending on what you are planning to do, one or the other will prove to be more efficient.

#### SR Latch

One of the most basic memory circuits, there are various ways to build them (wit NOR or NAND gates, or even other combinations). When the Set imput has a high value, the Q output will give a high value, and keep it that way until the Reset imput receives a high value. On the design below, if both imputs have a high value, the Latch will become unstable.

SR Latch with NOR gates:

Besiege note: After testing, if both S and R have a high value (regardless of Q value) R takes priority.

This design avoids the not desired state giving dominancy to the Reset.

#### D Latch

Having only one Data input, this latch will store the current D input level only when the Enable input has a high value. A D-latch may be considered as a one-input synchronous SR latch.

This latch will only receive new information when the clock is in a high value and will only keep it stored when the clock is low.

#### SR Flip Flop

Flip Flops are synchronous bistable components, which means that all information changes will occur only when the Control/Clock input is in a high value.

Besiege note: After testing, if both S and R have a high value (regardless of Q value) R takes priority.

#### JK Flip Flop

This Flip Flop works the same way as an SR Flip Flop without the Not desired state. When both J and K inputs have a high value, the output will toggle its current state.

As soon as I find a circuit that can be built in Besiege, I will add it here, most probably it will need some mechanical elements.